School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

  • Unit Title

    Digital Electronics
  • Unit Code

    ENS2456
  • Year

    2016
  • Enrolment Period

    1
  • Version

    2
  • Credit Points

    15
  • Full Year Unit

    N
  • Mode of Delivery

    On Campus

Description

This unit presents a technology review of digital logic families. Memory functions, memory types, and the design of large memory arrays are explained and an introduction to FPGA and CPLB programmable logic devices is given. Digital design and analysis methods, top-down design, algorithmic state machines (ASM), synthesis of ASM, sequencing and control and CPU design are also covered. An introduction to VHDL, simulation and testing of digital systems is included.

Prerequisite Rule

Students must pass 1 unit from ENS1161, ENS1162

Equivalent Rule

Unit was previously coded ENS2256

Learning Outcomes

On completion of this unit students should be able to:

  1. Analyse and design simple CPU.
  2. Describe digital logic in VHDL language.
  3. Describe digital systems as algorithmic state machines and synthesize ASM.
  4. Design a test for digital system.
  5. Use modern engineering design environment.
  6. Use the building blocks of digital systems, including programmable logic devices.

Unit Content

  1. Algorithmic state machines (ASM); synthesis of ASM.
  2. Digital design and analysis methods; top-down design.
  3. Digital logic families technology review.
  4. Engineering design environment.
  5. Introduction to VHDL.
  6. Memory as major component of digital systems memory types, large memory arrays.
  7. Programmable logic devices FPGA, CPLB.
  8. Sequencing and control; design of CPU.
  9. Simulation and testing of digital systems.
  10. VHDL description of combinational and sequential logic.

Additional Learning Experience Information

Lectures and laboratories.

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant Board of Examiners.

ON CAMPUS
TypeDescriptionValue
TestIn class tests30%
ReportLaboratory reports20%
Examination ^End of semester examination50%

^ Mandatory to Pass

Text References

  • ^ Vahid, F. (2011). Digital design with RTL design, VHDL, and Verilog (2nd ed.). New Jersey: John Wiley.
  • Zwolinski, M. (2004). Digital system design with VHDL (2nd ed.). Sydney: Prentice Hall.
  • Brown, S., & Varnesic, Z. (2009). Fundamentals of digital logic with VHDL design (3rd ed.). Sydney: McGraw Hill.
  • Mano, M. M., & Ciletti, M.D. (2012). Digital design (5th ed.). New Jersey: Prentice-Hall International, Inc.
  • Rushton, A. (2011). VHDL for logic synthesis (3rd ed.). Brisbane, John Wiley & Sons, Inc.
  • Balabanian, N., & Carlson, B. (2001). Digital logic design principles. Brisbane: John Wiley & Sons, Inc.

^ Mandatory reference


Disability Standards for Education (Commonwealth 2005)

For the purposes of considering a request for Reasonable Adjustments under the Disability Standards for Education (Commonwealth 2005), inherent requirements for this subject are articulated in the Unit Description, Learning Outcomes and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the support for students with disabilities or medical conditions can be found at the Access and Inclusion website.

Academic Misconduct

Edith Cowan University has firm rules governing academic misconduct and there are substantial penalties that can be applied to students who are found in breach of these rules. Academic misconduct includes, but is not limited to:

  • plagiarism;
  • unauthorised collaboration;
  • cheating in examinations;
  • theft of other students' work;

Additionally, any material submitted for assessment purposes must be work that has not been submitted previously, by any person, for any other unit at ECU or elsewhere.

The ECU rules and policies governing all academic activities, including misconduct, can be accessed through the ECU website.

ENS2456|2|1

School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

  • Unit Title

    Digital Electronics
  • Unit Code

    ENS2456
  • Year

    2016
  • Enrolment Period

    2
  • Version

    2
  • Credit Points

    15
  • Full Year Unit

    N
  • Mode of Delivery

    On Campus

Description

This unit presents a technology review of digital logic families. Memory functions, memory types, and the design of large memory arrays are explained and an introduction to FPGA and CPLB programmable logic devices is given. Digital design and analysis methods, top-down design, algorithmic state machines (ASM), synthesis of ASM, sequencing and control and CPU design are also covered. An introduction to VHDL, simulation and testing of digital systems is included.

Prerequisite Rule

Students must pass 1 unit from ENS1161, ENS1162

Equivalent Rule

Unit was previously coded ENS2256

Learning Outcomes

On completion of this unit students should be able to:

  1. Analyse and design simple CPU.
  2. Describe digital logic in VHDL language.
  3. Describe digital systems as algorithmic state machines and synthesize ASM.
  4. Design a test for digital system.
  5. Use modern engineering design environment.
  6. Use the building blocks of digital systems, including programmable logic devices.

Unit Content

  1. Algorithmic state machines (ASM); synthesis of ASM.
  2. Digital design and analysis methods; top-down design.
  3. Digital logic families technology review.
  4. Engineering design environment.
  5. Introduction to VHDL.
  6. Memory as major component of digital systems memory types, large memory arrays.
  7. Programmable logic devices FPGA, CPLB.
  8. Sequencing and control; design of CPU.
  9. Simulation and testing of digital systems.
  10. VHDL description of combinational and sequential logic.

Additional Learning Experience Information

Lectures and laboratories.

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant Board of Examiners.

ON CAMPUS
TypeDescriptionValue
TestIn class tests30%
ReportLaboratory reports20%
Examination ^End of semester examination50%

^ Mandatory to Pass

Text References

  • ^ Vahid, F. (2011). Digital design with RTL design, VHDL, and Verilog (2nd ed.). New Jersey: John Wiley.
  • Rushton, A. (2011). VHDL for logic synthesis (3rd ed.). Brisbane, John Wiley & Sons, Inc.
  • Brown, S., & Varnesic, Z. (2009). Fundamentals of digital logic with VHDL design (3rd ed.). Sydney: McGraw Hill.
  • Balabanian, N., & Carlson, B. (2001). Digital logic design principles. Brisbane: John Wiley & Sons, Inc.
  • Zwolinski, M. (2004). Digital system design with VHDL (2nd ed.). Sydney: Prentice Hall.
  • Mano, M. M., & Ciletti, M.D. (2012). Digital design (5th ed.). New Jersey: Prentice-Hall International, Inc.

^ Mandatory reference


Disability Standards for Education (Commonwealth 2005)

For the purposes of considering a request for Reasonable Adjustments under the Disability Standards for Education (Commonwealth 2005), inherent requirements for this subject are articulated in the Unit Description, Learning Outcomes and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the support for students with disabilities or medical conditions can be found at the Access and Inclusion website.

Academic Misconduct

Edith Cowan University has firm rules governing academic misconduct and there are substantial penalties that can be applied to students who are found in breach of these rules. Academic misconduct includes, but is not limited to:

  • plagiarism;
  • unauthorised collaboration;
  • cheating in examinations;
  • theft of other students' work;

Additionally, any material submitted for assessment purposes must be work that has not been submitted previously, by any person, for any other unit at ECU or elsewhere.

The ECU rules and policies governing all academic activities, including misconduct, can be accessed through the ECU website.

ENS2456|2|2