Handbook : Unit informationEdith Cowan University

School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

• Unit Title

  Digital Electronics

• Unit Code

  ENS2456

• Year

  2021

• Enrolment Period

  1

• Version

  2

• Credit Points

  15

• Full Year Unit

  N

• Mode of Delivery

  On Campus
  Online

• Unit Coordinator

  Dr Quoc Viet PHUNG

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Description

This unit presents a technology review of digital logic families. Memory functions, memory types, and the design of large memory arrays are explained and an introduction to FPGA and CPLB programmable logic devices is given. Digital design and analysis methods, top-down design, algorithmic state machines (ASM), synthesis of ASM, sequencing and control and CPU design are also covered. An introduction to VHDL, simulation and testing of digital systems is included.

Prerequisite Rule

Students must pass 1 unit from ENS1161, ENS1162

Equivalent Rule

Unit was previously coded ENS2256

Learning Outcomes

On completion of this unit students should be able to:

1. Analyse and design simple CPU.
2. Describe digital logic in VHDL language.
3. Describe digital systems as algorithmic state machines and synthesize ASM.
4. Design a test for digital system.
5. Use modern engineering design environment.
6. Use the building blocks of digital systems, including programmable logic devices.

Unit Content

1. Algorithmic state machines (ASM); synthesis of ASM.
2. Digital design and analysis methods; top-down design.
3. Digital logic families technology review.
4. Engineering design environment.
5. Introduction to VHDL.
6. Memory as major component of digital systems memory types, large memory arrays.
7. Programmable logic devices FPGA, CPLB.
8. Sequencing and control; design of CPU.
9. Simulation and testing of digital systems.
10. VHDL description of combinational and sequential logic.

Learning Experience

ON-CAMPUS

Students will attend on campus classes as well as engage in learning activities through ECUs LMS

For more information see the Semester Timetable

ONLINE

Students will engage in learning experiences through ECUs LMS as well as additional ECU l

Additional Learning Experience Information

Lectures and laboratories.

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant School Progression Panel.

^ Mandatory to Pass

Core Reading(s)

• Vahid, Frank. (2011). Digital design with RTL design, Verilog and VHDL (2. ed.). Hoboken, NJ: Wiley. Retrieved from https://ecu.on.worldcat.org/oclc/401167870

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