School: Engineering

This unit information may be updated and amended immediately prior to semester. To ensure you have the correct outline, please check it again at the beginning of semester.

  • Unit Title

    Digital Electronics
  • Unit Code

    ENS6154
  • Year

    2025
  • Enrolment Period

    1
  • Version

    3
  • Credit Points

    15
  • Full Year Unit

    N
  • Mode of Delivery

    On Campus
  • Unit Coordinator

    Dr Quoc PHUNG

Description

This unit provides students with an introduction to digital electronics. Memory functions, memory types, and the design of large memory arrays are explained and programmable logic devices are introduced. Digital design and analysis methods, top-down design, Algorithmic State Machines (ASM), synthesis of ASM, sequencing and control and Central Processing Unit (CPU) design are covered. An introduction to Hardware Description Language (HDL), and simulation and testing of digital systems is also included.

Equivalent Rule

Unit was previously coded ENS5256

Learning Outcomes

On completion of this unit students should be able to:

  1. Apply Boolean algebra theory to the design of digital circuits.
  2. Apply digital electronic principles and Hardware Description Language (HDL), encompassing the design of digital systems with combinational circuits, sequential circuits, and Finite State Machines (FSMs).
  3. Integrate standard digital circuit building blocks, including programmable logic devices and Register Transfer Level (RTL) abstractions to implement complex digital systems such as Central Processing Units (CPUs).
  4. Use modern engineering design tools (e.g. Vivado, Matlab, HDL) to simulate, implement, and test the operations of digital systems.
  5. Evaluate advanced technologies and new developments in the field of digital electronics and reflect critically on their significance to engineering practice.

Unit Content

  1. Boolean algebra and logic gates.
  2. Combinational logic simplification.
  3. Combinational functional blocks.
  4. Sequential logic circuits.
  5. Sequential logic design.
  6. Hardware Description Languages (HDLs).
  7. Memory and programmable logic devices.
  8. Register Transfer Level (RTL) design.
  9. Optimisation and trade-offs in digital system design.
  10. Programmable processors.
  11. Interfacing the analogue and digital domains.
  12. Design for Test (DFT) and Joint Testing Action Group (JTAG), scan pass, and Built-In-Self-Test (BIST) advanced testing techniques.

Learning Experience

Students will attend on campus classes as well as engage in learning activities through ECU's LMS

JoondalupMount LawleySouth West (Bunbury)
Semester 113 x 2 hour labNot OfferedNot Offered
Semester 113 x 2 hour lectureNot OfferedNot Offered
Semester 113 x 1 hour tutorialNot OfferedNot Offered

For more information see the Semester Timetable

Assessment

GS1 GRADING SCHEMA 1 Used for standard coursework units

Students please note: The marks and grades received by students on assessments may be subject to further moderation. All marks and grades are to be considered provisional until endorsed by the relevant School Progression Panel.

ON CAMPUS
TypeDescriptionValue
TestIn class tests30%
Laboratory Work ^Laboratory work and reports20%
PresentationResearch seminar10%
Examination ^End of semester examination40%

^ Mandatory to Pass


Disability Standards for Education (Commonwealth 2005)

For the purposes of considering a request for Reasonable Adjustments under the Disability Standards for Education (Commonwealth 2005), inherent requirements for this subject are articulated in the Unit Description, Learning Outcomes and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the support for students with disabilities or medical conditions can be found at the Access and Inclusion website.

Assessment

Students please note: The marks and grades received by students on assessments may be subject to further moderation. Informal vivas may be conducted as part of an assessment task, where staff require further information to confirm the learning outcomes have been met. All marks and grades are to be considered provisional until endorsed by the relevant School Progression Panel.

Academic Integrity

Integrity is a core value at Edith Cowan University, and it is expected that ECU students complete their assessment tasks honestly and with acknowledgement of other people's work as well as any generative artificial intelligence tools that may have been used. This means that assessment tasks must be completed individually (unless it is an authorised group assessment task) and any sources used must be referenced.

Breaches of academic integrity can include:

Plagiarism

Copying the words, ideas or creative works of other people or generative artificial intelligence tools, without referencing in accordance with stated University requirements. Students need to seek approval from the Unit Coordinator within the first week of study if they intend to use some of their previous work in an assessment task (self-plagiarism).

Unauthorised collaboration (collusion)

Working with other students and submitting the same or substantially similar work or portions of work when an individual submission was required. This includes students knowingly providing others with copies of their own work to use in the same or similar assessment task(s).

Contract cheating

Organising a friend, a family member, another student or an external person or organisation (e.g. through an online website) to complete or substantially edit or refine part or all of an assessment task(s) on their behalf.

Cheating in an exam

Using or having access to unauthorised materials in an exam or test.

Serious outcomes may be imposed if a student is found to have committed one of these breaches, up to and including expulsion from the University for repeated or serious acts.

ECU's policies and more information about academic integrity can be found on the student academic integrity website.

All commencing ECU students are required to complete the Academic Integrity Module.

Assessment Extension

In some circumstances, Students may apply to their Unit Coordinator to extend the due date of their Assessment Task(s) in accordance with ECU's Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000001386.

Special Consideration

Students may apply for Special Consideration in respect of a final unit grade, where their achievement was affected by Exceptional Circumstances as set out in the Assessment, Examination and Moderation Procedures - for more information visit https://askus2.ecu.edu.au/s/article/000003318.

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